1. Field of the Invention
This invention relates to semiconductor devices and more particularly to BiCMOS transistor devices and methods of manufacture thereof.
2. Description of Related Art
U.S. Pat. No. 5,793,085 of Vajana et al. for xe2x80x9cBipolar Transistor Compatible with CMOS Processesxe2x80x9d shows a BiCMOS process with ion implanted source/drain and base regions.
U.S. Pat. No. 5,681,765 of Darmawan for xe2x80x9cProcess for Fabricating Single Polysilicon High Performance BiCMOSxe2x80x9d shows a BiCMOS processes with a patterned photoresist layer 80 with an opening above a polysilicon layer 78 with a thickness of about 3250 xc3x85. Dopant 44 is implanted through the opening in the photoresist layer to form a base-emitter region 84 for an eventual bipolar transistor in a tub 68 in an epitaxial layer 60.
U.S. Pat. No. 5,606,192 of Harada for xe2x80x9cSemiconductor Integrated Circuits Having Bipolar Transistors and LDD-Structured MOSFETxe2x80x9d show BiCMOS processes with polysilicon layers and ion implanting boron ions to form an N-type region in a polysilicon emitter electrode layer 23 formed above a gate oxide layer 12, which in turn is formed above a base layer 19 formed in an N-type epitaxial layer 4 in a P-silicon substrate 1.
U.S. Pat. No. 4,902,639 of Ford for xe2x80x9cProcess for Making BiCMOS Integrated Circuit Having a Shallow Trench Bipolar Transistor with Vertical Base Contactsxe2x80x9d describes a BiCMOS process, but makes a reference to the NMOS region 27 at Col. 3, lines 23-41, to an intermediate stage of manufacturing the NMOS region 27. A second polysilicon layer is deposited on a previous polysilicon layer. The second polysilicon layer is then heavily doped to become a polysilicon N+ layer with an N+ dopant. Alternatively the polysilicon is deposited as a heavily doped layer by an in situ process. Then in NMOS region 27, using a portion of the second polysilicon layer which is now heavily doped polysilicon N+ layer 40, a buried contact region 41 is formed in a P-well region 16 by diffusion, as the result of a high temperature anneal. In Col. 4, lines 4-43, a trench is formed where the NPN transistor is to be formed. First an active base region 67 is formed by implanting boron in the N-well 19. Oxide sidewalls 68 are formed in the trench. A polysilicon emitter 69 is deposited in the trench between the oxide sidewalls 68. Then emitter 69 is doped N-type using masks and implants. By this process or an anneal, a very shallow N-type emitter junction is formed in the active base region from the doping of the polysilicon emitter 69.
U.S. Pat. No. 5,504,362 of Pelella et al., xe2x80x9cElectrostatic Discharge Protection Devicexe2x80x9d in Cols. 7 and 8 and FIG. 2 teaches outdiffusion from N+ polysilicon emitter contact 48/P+ polysilicon base contact 44 to form N+ emitter outdiffusion region 39/P+ base outdiffusion region 40 of an NPN bipolar transistor 15C in a BiCMOS device.
U.S. Pat. No. 5,652,154 of Komuro for xe2x80x9cMethod for Manufacturing BIMOS Devicexe2x80x9d shows a process for manufacturing a BiCMOS device. At Col. 5, lines 7-37, an intrinsic base region 109 is formed by ion implantation of a P-type dopant comprising boron into an N-type silicon region C of a P-type silicon substrate 101. Later in the process there is an ion implantation of the polysilicon layer which is first xe2x80x9cmodified to have an N-type conductivityxe2x80x9d by driving dopant from a doped glass layer or by ion implanting N-type dopant into the polysilicon. Then the doped polysilicon is formed into gate electrodes 112a-112c which are to be used to form FET devices in areas A and B and a bipolar device in area C. Then xe2x80x9c . . . in area C, the polysilicon layer is left as an emitter electrode 112c above an emitter diffused region forming area for the bipolar transistor.xe2x80x9d The next step is a heat treatment step employed to form an N-type emitter region 113 in the P type intrinsic region 109. (Col. 5, lines 38-59).
When the gates of CMOS transistors are scaled to less than 100 nm, the gate oxide thicknesses will be around 5 xc3x85 to 40 xc3x85. Under such circumstances, the gate structures of bipolar devices and MOS devices become more similar than the large geometry devices.
In accordance with this invention, a simple approach to structure of bipolar devices and MOS devices is provided. The present invention is very compatible with CMOS process with minimum additional steps to form the self-aligned bipolar transistors in a standard CMOS process.
In accordance with this invention, a semi-conductor device comprises dielectric, isolation structures formed in a top surface of a silicon semiconductor substrate, separating the substrate into emitter, NMOS and PMOS areas. A gate oxide layer is superjacent to (overlies) the isolation structures on the top surface of the silicon semiconductor substrate. A conductive polysilicon layer is superjacent to the thin silicon oxide layer. Emitter dopant has been ion implanted into a portion of the conductive polysilicon layer over the emitter area of the substrate. The substrate including the thin silicon oxide layer was annealed driving dopant from the polysilicon layer into an emitter region in the emitter area in the substrate. Doped source/drain regions are formed in the NMOS and PMOS areas of the substrate, and a base region is formed in the emitter area of the substrate as part of an NPN device. Preferably, annealing was performed by rapid thermal annealing. The gate oxide has a thickness from about 5 xc3x85 to about 40 xc3x85. The isolation structures are trenches formed in the substrate filled with silicon oxide dielectric.
In accordance with another aspect of this invention, a semiconductor device comprises dielectric, isolation structures formed in a top surface of a silicon semiconductor substrate, separating the substrate into emitter, NMOS and PMOS areas. A gate oxide layer is superjacent to (overlies) the isolation structures on the top surface of the silicon semiconductor substrate. A conductive polysilicon layer is superjacent to the thin silicon oxide layer. Emitter dopant has been ion implanted into a portion of the conductive polysilicon layer over the emitter area of the substrate. The substrate including the thin silicon oxide layer was annealed driving dopant from the polysilicon layer into an emitter region in the emitter area in the substrate. Doped source/drain regions are formed in the NMOS and PMOS areas of the substrate, and a base region is formed in the emitter area of the substrate as part of an NPN device. Preferably, annealing was performed by rapid thermal annealing. The gate oxide has a thickness from about 5 xc3x85 to about 40 xc3x85. The isolation structures are trenches formed in the substrate filled with silicon oxide dielectric.